Soft Error Reliability of VLSI Circuits by Behnam Ghavami & Mohsen Raji

Author:Behnam Ghavami & Mohsen Raji
Language: eng
Format: epub
ISBN: 9783030516109
Publisher: Springer International Publishing

As shown in Fig. 5.1, the proposed approach consists of two main steps: (1) instrumentation and (2) FPGA run. In the instrumentation step, some modifications are done on the circuit in order to maximize the efficiency when running on FPGA. For this purpose, the circuit is first split into several independent sub-circuits such that they could fit on the FPGA. Then, a developed tool generates an HDL code of the sub-circuit based on a probability propagation model. The generated code will be used as an input for Xilinx commercial tools. In the last part of this step, a bit file containing the information about the circuit and the fault locations is downloaded on FPGA. In the second step, one or several sub-circuits (based on their sizes) are ran on FPGA to estimate the circuit SER. Since the proposed approach avoids unnecessary iterations and exploits FPGA for processing instead of CPU, it is expected that the introduced approach be much faster than the traditional ones.

Fig. 5.1An overview of the proposed approach composed of instrumentation phase (including the circuit partitioning, applying the probability rules, and generating the bit file for FPGA execution) and the FPGA run phase (including the execution of the proposed algorithm on FPGA and sending the results to the host computer)

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